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CS4344/5/6/8
10-pin, 24-Bit, 192 kHz Stereo D/A Converter
Features
! Multi-bit Delta-Sigma Modulator ! 24-bit Conversion ! Automatically Detects Sample Rates up to
Description
The CS4344 family members are complete, stereo digital-to-analog output systems including interpolation, multi-bit D/A conversion and output analog filtering in a 10-pin package. The CS4344/5/6/8 support all major audio data interface formats, and the individual devices differ only in the supported interface format. The CS4344 family is based on a fourth order multi-bit delta-sigma modulator with a linear analog low-pass filter. This family also includes auto-speed mode detection using both sample rate and master clock ratio as a method of auto-selecting sampling rates between 2 kHz and 200 kHz. The CS4344 family contains on-chip digital de-emphasis, operates from a single +3.3 V or +5 V power supply, and requires minimal support circuitry. These features are ideal for DVD players & recorders, digital televisions, home theater and set top box products, and automotive audio systems. The CS4344 family is available in a 10-pin TSSOP package in both Commercial (-10 to +85 C) and Automotive grades (-40 to +85 C). Please see Section 8. "Ordering Information" on page 23 for complete details.
192 kHz.
! 105 dB Dynamic Range ! -90 dB THD+N ! Low Clock-Jitter Sensitivity ! Single +3.3 V or +5 V Power Supply ! Filtered Line-Level Outputs ! On-chip Digital De-emphasis ! PopguardTM Technology ! Small 10-pin TSSOP Package
3.3 V or 5 V
De-emphasis
Interpolation Filter
Multibit Modulator
Switched Capacitor DAC and Filter Switched Capacitor DAC and Filter Internal Voltage Reference
Left Output
Serial Audio Input
PCM Serial Interface
Interpolation Filter
Multibit Modulator
Right Output
http://www.cirrus.com
Copyright (c) Cirrus Logic, Inc. 2005 (All Rights Reserved)
SEPTEMBER '05 DS613F1
CS4344/5/6/8
TABLE OF CONTENTS
1. PIN DESCRIPTIONS .............................................................................................................................. 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 5 SPECIFIED OPERATING CONDITIONS ................................................................................................... 5 ABSOLUTE MAXIMUM RATINGS .............................................................................................................. 5 DAC ANALOG CHARACTERISTICS .......................................................................................................... 6 DAC ANALOG CHARACTERISTICS - ALL MODES .................................................................................. 6 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ............................................. 7 DIGITAL INPUT CHARACTERISTICS ....................................................................................................... 8 POWER AND THERMAL CHARACTERISTICS ........................................................................................ 8 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE ........................................................... 9 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 11 4. APPLICATIONS ................................................................................................................................... 12 4.1 Master Clock ................................................................................................................................. 12 4.2 Serial Clock .................................................................................................................................. 12 4.2.1 External Serial Clock Mode ................................................................................................. 12 4.2.2 Internal Serial Clock Mode .................................................................................................. 12 4.3 De-Emphasis ................................................................................................................................ 15 4.4 Initialization and Power-Down ...................................................................................................... 15 4.5 Output Transient Control .............................................................................................................. 15 4.5.1 Power-Up ............................................................................................................................ 15 4.5.2 Power-Down ........................................................................................................................ 15 4.6 Grounding and Power Supply Decoupling .................................................................................... 17 4.7 Analog Output and Filtering .......................................................................................................... 17 5. FILTER PLOTS ..................................................................................................................................... 18 6. PARAMETER DEFINITIONS ................................................................................................................ 21 7. PACKAGE DIMENSIONS .................................................................................................................... 22 8. ORDERING INFORMATION ................................................................................................................ 23 8.1 Functional Compatibility ............................................................................................................... 23 8.2 Selection Guide ............................................................................................................................ 23 9. REVISION HISTORY ............................................................................................................................ 24
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CS4344/5/6/8
LIST OF FIGURES
Figure 1. Output Test Load ......................................................................................................................... 8 Figure 2. Maximum Loading ........................................................................................................................ 8 Figure 3. External Serial Mode Input Timing ............................................................................................. 10 Figure 4. Internal Serial Mode Input Timing .............................................................................................. 11 Figure 5. Internal Serial Clock Generation ................................................................................................ 11 Figure 6. Recommended Connection Diagram ......................................................................................... 12 Figure 7. CS4344 Data Format (I2S) ......................................................................................................... 14 Figure 8. CS4345 Data Format (Left Justified) ......................................................................................... 14 Figure 9. CS4346 Data Format (Right Justified 24) .................................................................................. 15 Figure 10. CS4348 Data Format (Right Justified 16) ................................................................................ 15 Figure 11. De-Emphasis Curve (Fs = 44.1kHz) ........................................................................................ 16 Figure 12. CS4344/5/6/8 Initialization and Power-down Sequence .......................................................... 17 Figure 13. Single Speed Stopband Rejection ........................................................................................... 19 Figure 14. Single Speed Transition Band ................................................................................................. 19 Figure 15. Single Speed Transition Band ................................................................................................. 19 Figure 16. Single Speed Passband Ripple ............................................................................................... 19 Figure 17. Double Speed Stopband Rejection .......................................................................................... 20 Figure 18. Double Speed Transition Band ................................................................................................ 20 Figure 19. Double Speed Transition Band ................................................................................................ 20 Figure 20. Double Speed Passband Ripple .............................................................................................. 20 Figure 21. Quad Speed Stopband Rejection ............................................................................................ 21 Figure 22. Quad Speed Transition Band ................................................................................................... 21 Figure 23. Quad Speed Transition Band ................................................................................................... 21 Figure 24. Quad Speed Passband Ripple ................................................................................................. 21
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CS4344/5/6/8 1. PIN DESCRIPTIONS
SDIN DEM/SCLK LRCK MCLK VQ
1 2 3 4 5 10 9 8 7 6
AOUTR VA GND AOUTL FILT+
Pin Name
SDIN DEM/SCLK LRCK MCLK VQ FILT+ AOUTL GND VA AOUTR
#
1 2 3 4 5 6 7 8 9
Pin Description
Serial Audio Data Input (Input) - Input for two's complement serial audio data. De-Emphasis/External Serial Clock Input (Input) - used for de-emphasis filter control or external serial clock input. Left Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling circuits. Left Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics specification table. Ground (Input) - ground reference. Analog Power (Input) - Positive power for the analog and digital sections.
10 Right Channel Analog Output (Output) - The full scale analog output level is specified in the Analog Characteristics specification table.
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CS4344/5/6/8 2. CHARACTERISTICS AND SPECIFICATIONS
(All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltage and TA = 25C.)
SPECIFIED OPERATING CONDITIONS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply Specified Temperature Range -CZZ -DZZ
Symbol
VA TA
Min
4.75 3.00 -10 -40
Nom
5.0 3.3 -
Max
5.25 3.47 +70 +85
Units
V V C C
ABSOLUTE MAXIMUM RATINGS
(AGND = 0 V; all voltages with respect to ground.)
Parameters
DC Power Supply Input Current, Any Pin Except Supplies Digital Input Voltage Ambient Operating Temperature (power applied) Storage Temperature
Symbol
VA Iin VIND Top Tstg
Min
-0.3 -0.3 -55 -65
Max
6.0 10 VA+0.4 125 150
Units
V mA V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS4344/5/6/8 DAC ANALOG CHARACTERISTICS
(Full-Scale Output Sine Wave, 997 Hz (Note 1), Fs = 48/96/192 kHz; Test load RL = 3 k, CL = 10 pF (Figure 1). Measurement Bandwidth 10 Hz to 20 kHz, unless otherwise specified.)
5 V Nom Parameter
Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB A-weighted unweighted A-weighted unweighted 0 dB -20 dB -60 dB 0 dB -20 dB -60 dB
3.3 V Nom Max
-85 -76 -36 -84 -67 -27 -82 -72 -32 -82 -63 -23
Min
99 96 90 87 95 92 86 83 -
Typ
105 102 96 93 -90 -82 -42 -90 -73 -33 105 102 96 93 -90 -82 -42 -90 -73 -33
Min
97 94 90 87 93 90 86 83 -
Typ
103 100 96 93 -90 -80 -40 -90 -73 -33 103 100 96 93 -90 -80 -40 -90 -73 -33
Max
-85 -74 -34 -84 -67 -27 -82 -70 -30 -82 -63 -23
Unit
dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB dB
Dynamic Performance for CS4344/5/6/8-CZZ (-10 to 70C)
16-Bit
Dynamic Performance for CS4344/5-DZZ (-40 to 85C)
Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit
16-Bit
Notes:
1. One-half LSB of triangular PDF dither added to data.
DAC ANALOG CHARACTERISTICS - ALL MODES
Parameter
Interchannel Isolation (1 kHz)
Symbol
Min
0.60*VA
Typ
100 0.1 100 0.65*VA 0.5*VA 10 100 3 100 100
Max
0.25 0.70*VA -
Unit
dB dB ppm/C Vpp VDC A A k pF
DC Accuracy
Interchannel Gain Mismatch Gain Drift
Analog Output
Full Scale Output Voltage Quiescent Voltage Max DC Current draw from an AOUT pin Max Current draw from VQ Max AC-Load Resistance (see Figure 2 on page 8) Max Load Capacitance (see Figure 2 on page 8) Output Impedance VQ IOUTmax IQmax RL CL ZOUT -
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CS4344/5/6/8 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
(The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs.) See (Note 6)
Parameter Symbol Min Typ Max Unit Combined Digital and On-chip Analog Filter ResponseSingle-Speed Mode
Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay De-emphasis Error (Note 5) Fs = 32 kHz Fs = 44.1 kHz Fs = 48 kHz (Note 3) tgd to -0.1 dB corner to -3 dB corner 0 0 -.175 .5465 50 10/Fs .35 .4992 +.01 +1.5/+0 +.05/-.25 -.2/-.4 Fs Fs dB Fs dB s dB dB dB
Combined Digital and On-chip Analog Filter ResponseDouble-Speed Mode
Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 3) tgd to +0.1 dB corner to -3 dB corner 0 0 -.15 .5770 55 5/Fs .22 .501 +.15 Fs Fs dB Fs dB s
Combined Digital and On-chip Analog Filter ResponseQuad-Speed Mode
Passband (Note 2) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Group Delay (Note 3) tgd to -0.1 dB corner to -3 dB corner 0 0 -.12 0.7 51 2.5/Fs 0.110 0.469 +0 Fs Fs dB Fs dB s
Notes:
2. Response is clock dependent and will scale with Fs. 3. For Single-Speed Mode, the Measurement Bandwidth is 0.5465 Fs to 3 Fs. For Double-Speed Mode, the Measurement Bandwidth is 0.577 Fs to 1.4 Fs. For Quad-Speed Mode, the Measurement Bandwidth is 0.7 Fs to 1 Fs. 4. Refer to Figure 2. 5. De-emphasis is available only in Single-Speed Mode. 6. Amplitude vs. Frequency plots of this data are available in "Filter Plots" on page 18.
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CS4344/5/6/8 DIGITAL INPUT CHARACTERISTICS
Parameters
High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance (% of VA) (% of VA) (Note 7)
Symbol
VIH VIL Iin
Min
60% -
Typ
8
Max
30% 10 -
Units
V V A pF
7. Iin for LRCK is 20 A max.
POWER AND THERMAL CHARACTERISTICS
5 V Nom Parameters Power Supplies
Power Supply Current (Note 8) Power Dissipation normal operation power-down state (Note 9) normal operation power-down state(Note 9) Package Thermal Resistance Power Supply Rejection Ratio (Note 8) (1 kHz) (60 Hz) IA IA 22 220 110 1.1 95 50 40 30 150 16 100 53 0.33 95 50 40 21 69 mA A mW mW C/Watt dB dB
3.3 V Nom Max Min Typ Max Units
Symbol
Min
Typ
JA PSRR
8. Current consumption increases with increasing FS and increasing MCLK. Typ and Max values are based on highest FS and highest MCLK. Variance between speed modes is small. 9. Power down mode is defined when all clock and data lines are held static. 10. Valid with the recommended capacitor values on VQ and FILT+ as shown in the typical connection diagram in Section 3.
3.3 F AO U Tx R C V o ut
L
L
AG N D
Figure 1. Output Test Load
125 Capacitive Load -- C L (pF) 100 75 50 25 Safe Operating Region
2.5 3
5
10
15
20
Resistive Load -- RL (k )
Figure 2. Maximum Loading
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CS4344/5/6/8 SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency MCLK Duty Cycle Input Sample Rate (Note 11) All MCLK/LRCK ratios combined 256x, 384x, 1024x 256x, 384x 512x, 768x 1152x 128x, 192x 64x, 96x 128x, 192x Fs
Symbol
Min
0.512 45 2 2 84 42 30 50 100 168 45
Typ
-
Max
50 55 200 50 134 67 34 100 200 200
Units
MHz % kHz kHz kHz kHz kHz kHz kHz kHz % ns ns % ns ns ns ns % ns s
External SCLK Mode
LRCK Duty Cycle (External SCLK only) SCLK Pulse Width Low SCLK Pulse Width High SCLK Duty Cycle SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tslrd tslrs tsdlrs tsdh (Note 12) (Note 13) tsclkw tsclkr tsclkl tsclkh 50 50 50 tsclkw ----------------2 55 55 20 20 45 20 20 20 20 10 9 --------------SCLK -
Internal SCLK Mode
LRCK Duty Cycle (Internal SCLK only) SCLK Period
SCLK rising to LRCK edge
-
SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time MCLK / LRCK =1152, 1024, 512, 256, 128, or 64 SCLK rising to SDIN hold time MCLK / LRCK = 768, 384, 192, or 96
tsdlrs
10 9 --------------------- + 10 ( 512 )Fs 10 9 --------------------- + 15 ( 512 )Fs 10 9 --------------------- + 15 ( 384 )Fs
-
ns
tsdh
-
-
ns
tsdh
-
-
ns
11. Not all sample rates are supported for all clock ratios. See Table 1, "Common Clock Frequencies," on page 12 for supported ratio's and frequencies. 12. In Internal SCLK Mode, the Duty Cycle must be 50% +/- 1/2 MCLK Period. 13. The SCLK / LRCK ratio may be either 32, 48, 64, or 72. This ratio depends on part type and MCLK/LRCK ratio. (See Figures 7-9)
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CS4344/5/6/8
LRCK t slrd t slrs t sclkl t sclkh
SCLK t sdlrs
SDATA
t sdh
Figure 3. External Serial Mode Input Timing
LRCK
t sclkr
SDATA t sclkw t sdlrs *INTERNAL SCLK t sdh
The SCLK pulses shown are internal to the CS4344/5/6/8.
Figure 4. Internal Serial Mode Input Timing
LRCK
MCLK
1 *INTERNAL SCLK N 2 N
SDATA
* The SCLK pulses shown are internal to the CS4344/5/6/8. N equals MCLK divided by SCLK
Figure 5. Internal Serial Clock Generation
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CS4344/5/6/8 3. TYPICAL CONNECTION DIAGRAM
Note* = This circuitry is intended for applications where the CS4344/5/6/8 connects directly to an unbalanced output of the design. For internal routing applications please see the DAC analog output characteristics for loading limitations.
+ 9 VA 0.1 F 1 F
+3.3 V to +5 V
Note*
1 Audio Data Processor 2 3 SDIN DEM/SCLK LRCK 10 k AOUTL 7 + C Rext 3.3 F 470 Left Audio Output
CS4344 CS4345 AOUTR 10 CS4346 CS4348
3.3 F + 10 k
470
Right Audio Output
C
Rext
External Clock
4
FILT+ MCLK
6 10 F C= Rext + 470 4Fs(Rext
For best 20 kHz response 470)
+ VQ 5 0.1 F
AGND 8
*3.3 F or *10 F
*Popguard ramp can be adjusted by selecting this capacitor value to be 3.3 F to give 250 ms ramp time or 10 F to give a 420 ms ramp time.
Figure 6. Recommended Connection Diagram
+
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CS4344/5/6/8 4. APPLICATIONS
The CS4344 family accepts data at standard audio sample rates including 48, 44.1 and 32 kHz in SSM, 96, 88.2 and 64 kHz in DSM, and 192, 176.4 and 128 kHz in QSM. Audio data is input via the serial data input pin (SDIN). The Left/Right Clock (LRCK) determines which channel is currently being input on SDIN, and the optional Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4344/5/6/8 differ in serial data formats as shown in Figures 7-10.
4.1
Master Clock
MCLK/LRCK must be an integer ratio as shown in Table 1. The LRCK frequency is equal to Fs, the frequency at which words for each channel are input to the device. The MCLK-to-LRCK frequency ratio and speed mode is detected automatically during the initialization sequence by counting the number of MCLK transitions during a single LRCK period and by detecting the absolute speed of MCLK. Internal dividers are set to generate the proper clocks. Table 1 illustrates several standard audio sample rates and the required MCLK and LRCK frequencies. Please note there is no required phase relationship, but MCLK, LRCK and SCLK must be synchronous.
MCLK (MHz) 256x 384x
LRCK 64x 96x 128x (kHz) 32 44.1 48 8.1920 64 11.2896 88.2 12.2880 96 8.1920 12.2880 128 176.4 11.2896 16.9344 22.5792 12.2880 18.4320 24.5760 192 Mode QSM
192x
512x
768x
1024x
1152x
12.2880 16.9344 18.4320 33.8680 36.8640
8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 22.5792 33.8680 24.5760 36.8640 32.7680 49.1520 DSM
22.5792 24.5760 32.7680 -
32.7680 33.8680 45.1580 36.8640 49.1520 49.1520 SSM
36.8640 -
Table 1. Common Clock Frequencies
4.2
Serial Clock
The serial clock controls the shifting of data into the input data buffers. The CS4344 family supports both external and internal serial clock generation modes. Refer to Figures 7-10 for data formats.
4.2.1
External Serial Clock Mode
The CS4344 family will enter the External Serial Clock Mode when 16 low to high transitions are detected on the DEM/SCLK pin during any phase of the LRCK period. When this mode is enabled, the Internal Serial Clock Mode and de-emphasis filter cannot be accessed. The CS4344 family will switch to Internal Serial Clock Mode if no low to high transitions are detected on the DEM/SCLK pin for 2 consecutive frames of LRCK. Refer to Figure 12.
4.2.2
Internal Serial Clock Mode
In the Internal Serial Clock Mode, the serial clock is internally derived and synchronous with MCLK and LRCK. The SCLK/LRCK frequency ratio is either 32, 48, 64, or 72 depending upon data format. Operation in this mode is identical to operation with an external serial clock synchronized with LRCK. This mode allows access to the digital de-emphasis function. Refer to Figures 7 - 12 for details.
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CS4344/5/6/8
Left Channel Right Channel
LRCK SCLK
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
IS, 16-Bit data and INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 IS, Up to 24-Bit data and INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 IS, Up to 24-Bit data and INT SCLK = 72 Fs if MCLK/LRCK = 1152
External SCLK Mode
IS, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 7. CS4344 Data Format (I2S)
LRCK SCLK
Left Channel
Right Channel
SDATA
MSB -1 -2 -3 -4 -5
+5 +4 +3 +2 +1 LSB
MSB -1 -2 -3 -4
+5 +4 +3 +2 +1 LSB
Internal SCLK Mode
Left-Justified, up to 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152
External SCLK Mode
Left-Justified, up to 24-Bit Data Data Valid on Rising Edge of SCLK
Figure 8. CS4345 Data Format (Left Justified)
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CS4344/5/6/8
LRCK
Right Channel
Left Channel
SCLK
SDATA
0
23 22 21 20 19 18
76543210
23 22 21 20 19 18
76543210
Internal SCLK Mode
Right Justified, 24-Bit Data INT SCLK = 64 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152
32 clocks
External SCLK Mode
Right Justified, 24-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 48 Cycles per LRCK Period
Figure 9. CS4346 Data Format (Right Justified 24)
LRCK
Left Channel
Right Channel
SCLK
SDATA
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Internal32 clocks Mode SCLK
Right Justified, 16-Bit Data INT SCLK = 32 Fs if MCLK/LRCK = 1024, 512, 256, 128, or 64 INT SCLK = 48 Fs if MCLK/LRCK = 768, 384, 192, or 96 INT SCLK = 72 Fs if MCLK/LRCK = 1152
External SCLK Mode
Right Justified, 16-Bit Data Data Valid on Rising Edge of SCLK SCLK Must Have at Least 32 Cycles per LRCK Period
Figure 10. CS4348 Data Format (Right Justified 16)
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4.3 De-Emphasis
The CS4344 family includes on-chip digital de-emphasis. Figure 11 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate, Fs. The de-emphasis filter is active (inactive) if the DEM/SCLK pin is low (high) for 5 consecutive falling edges of LRCK. This function is available only in the internal serial clock mode
.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 11. De-Emphasis Curve (Fs = 44.1kHz)
4.4
Initialization and Power-Down
The Initialization and Power-down sequence flow chart is shown in Figure 12. The CS4344 family enters the Power-Down State upon initial power-up. The interpolation filters and delta-sigma modulators are reset, and the internal voltage reference, multi-bit digital-to-analog converters and switched-capacitor low-pass filters are powered down. The device will remain in the Power-down mode until MCLK and LRCK are present. Once MCLK and LRCK are detected, MCLK occurrences are counted over one LRCK period to determine the MCLK/LRCK frequency ratio. Power is then applied to the internal voltage reference. Finally, power is applied to the D/A converters and switched-capacitor filters, and the analog outputs will ramp to the quiescent voltage, VQ.
4.5
Output Transient Control
The CS4344 family uses PopguardTM technology to minimize the effects of output transients during powerup and power-down. This technique eliminates the audio transients commonly produced by single-ended single-supply converters when it is implemented with external DC-blocking capacitors connected in series with the audio outputs. To make best use of this feature, it is necessary to understand its operation.
4.5.1
Power-Up
When the device is initially powered-up, the audio outputs, AOUTL and AOUTR, are clamped to VQ which is initially low. After MCLK is applied the outputs begin to ramp with VQ towards the nominal quiescent voltage. This ramp takes approximately 250 ms with a 3.3 F cap connected to VQ (420 ms with a 10 F connected to VQ) to complete. The gradual voltage ramping allows time for the external DC-blocking capacitors to charge to VQ, effectively blocking the quiescent DC voltage. Once valid LRCK and SDIN are supplied (and SCLK if used) approximately 2000 sample periods later audio output begins.
4.5.2
Power-Down
To prevent audio transients at power-down the DC-blocking capacitors must fully discharge before turning off the power. In order to do this MCLK should be stopped for a period of about 250 ms for a 3.3 F cap connected to VQ (420 ms for a 10 F cap connected to VQ) before removing power. During this time voltage on VQ and the audio outputs discharge gradually to GND. If power is removed before this time period has passed a transient will occur when the VA supply drops below that of VQ. There is no minimum time for a power cycle, power may be re-applied at any time.
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CS4344/5/6/8
When changing clock ratio or sample rate it is recommended that zero data (or near zero data) be present on SDIN for at least 10 LRCK samples before the change is made. During the clocking change the DAC outputs will always be in a zero data state. If no zero audio is present at the time of switching, a slight click or pop may be heard as the DAC output automatically goes to it's zero data state.
USER: Apply Power
VQ and outputs ram p down
Power-Down State
VQ and outputs low
VQ and outputs ram p down
USER: Apply MCLK USER: Rem ove MCLK VQ and outputs ram p up USER: Rem ove MCLK
USER: Rem ove LRCK
W ait State
USER: Rem ove LRCK
USER: Apply LRCK
USER: change MCLK/LRCK ratio
MCLK/LRCK Ratio Detection
USER: change MCLK/LRCK ratio
USER: No SCLK
USER: Applied SCLK
SCLK m ode = internal
SCLK m ode = external
Norm al Operation De-em phasis available
Norm al Operation De-em phasis not available
Analog Output is Generated
Analog Output is Generated
Figure 12. CS4344/5/6/8 Initialization and Power-down Sequence
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4.6 Grounding and Power Supply Decoupling
As with any high resolution converter, the CS4344 family requires careful attention to power supply and grounding arrangements to optimize performance. Figure 6 shows the recommended power arrangement with VA connected to a clean +3.3 V or +5 V supply. For best performance, decoupling and filter capacitors should be located as close to the device package as possible with the smallest capacitors closest.
4.7
Analog Output and Filtering
The analog filter present in the CS4344 family is a switched-capacitor filter followed by a continuous time low pass filter. Its response, combined with that of the digital interpolator, is given in Figures 13 - 20. The recommended external analog circuitry is shown in the "Typical Connection Diagram" on page 11.
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CS4344/5/6/8 5. FILTER PLOTS
Figure 13. Single-Speed Stopband Rejection
Figure 14. Single-Speed Transition Band
0
-1
0.05
-2
0
-3
Amplitude dB
Amplitude dB
-4
-0.05
-5
-0. 1
-6
-0.15
-7
-0. 2
-8
-0.25
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency (normalized to Fs)
0.52
0.53
0.54
0.5 5
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 15. Single-Speed Transition Band
Figure 16. Single-Speed Passband Ripple
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Figure 17. Double-Speed Stopband Rejection
Figure 18. Double-Speed Transition Band
1 0 -1 -2
0.8 0.7 0.6 0.5
-3
Amplitude dB
-4 -5 -6 -7 -8 -9 - 10 0.45
Amplitude dB
0.46 0.47 0.48 0.49 0.5 0.51 Frequency (normalized to Fs) 0.52 0.53 0.54 0.55
0.4 0.3 0.2 0.1 0 -0. 1 -0. 2
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 19. Double-Speed Transition Band
Figure 20. Double-Speed Passband Ripple
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0
0
-10
-10
-20
-30
-20
-40 Amplitude (dB)
Amplitude (dB) -30
-50
-60
-40
-70
-50
-80
-60
-90
-100 0 0.1 0.2 0.3 0.4 0.5 0.6 Frequency(normalized to Fs) 0.7 0.8 0.9 1
0.35 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7 0.75
Figure 21. Quad-Speed Stopband Rejection
Figure 22. Quad-Speed Transition Band
0 -5 -10 -15 -20 -25 -30 -35 -40 -45 -50 0.4 0.45 0.5 0.55 0.6 Frequency(normalized to Fs) 0.65 0.7
0
-0. 5
Amplitude (dB)
Amplitude dB
-1 -1. 5 0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency (normalized to Fs)
0.35
0.4
0.45
0.5
Figure 23. Quad-Speed Transition Band
Figure 24. Quad-Speed Passband Ripple
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DS613F1
CS4344/5/6/8 6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N)
The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels.
Dynamic Range
The ratio of the full scale rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not effect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES17-1991, and the Electronic Industries Association of Japan, EIAJ CP-307.
Interchannel Isolation
A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels.
Interchannel Gain Mismatch
The gain difference between left and right channels. Units in decibels.
Gain Error
The deviation from the nominal full scale analog output for a full scale digital input.
Gain Drift
The change in gain value with temperature. Units in ppm/C.
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CS4344/5/6/8 7. PACKAGE DIMENSIONS 10LD TSSOP (3 mm BODY) PACKAGE DRAWING
N
D c E A2 A1
L
E11 A
e b END VIEW SIDE VIEW SEATING PLANE
L1
123
TOP VIEW
DIM A A1 A2 b c D E E1 e L L1
MIN -0 0.0295 0.0059 0.0031 ----0.0157 -0
INCHES NOM -----0.1181 BSC 0.1929 BSC 0.1181 BSC 0.0197 BSC 0.0236 0.0374 REF --
MAX 0.0433 0.0059 0.0374 0.0118 0.0091 ----0.0315 -8
MIN -0 0.75 0.15 0.08 ----0.40 -0
MILLIMETERS NOM -----3.00 BSC 4.90 BSC 3.00 BSC 0.50 BSC 0.60 0.95 REF --
NOTE MAX 1.10 0.15 0.95 0.30 0.23 ----0.80 -8
4, 5 2 3
Controlling Dimension is Millimeters Notes:
1. Reference document: JEDEC MO-187 2. D does not include mold flash or protrusions which is 0.15 mm max. per side. 3. E1 does not include inter-lead flash or protrusions which is 0.15 mm max per side. 4. Dimension b does not include a total allowable dambar protrusion of 0.08 mm max. 5. Exceptions to JEDEC dimension.
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DS613F1
CS4344/5/6/8 8. ORDERING INFORMATION
Product
CS4344 CS4345 CS4346 CS4348 24-Bit, 192 kHz Stereo D/A Converter 10-TSSOP Yes
Description
Package Pb-Free
Grade
Commercial Automotive Commercial Automotive Commercial
Temp Range
-10 to +70 C -40 to +85 C -10 to +70 C -40 to +85 C -10 to +70 C
Container
Tube or Tape and Reel
Order #
CS4344-CZZ CS4344-DZZ CS4345-CZZ CS4345-DZZ CS4346-CZZ CS4348-CZZ
8.1
Functional Compatibility
CS4334-KS CS4344-CZZ CS4335-KS CS4345-CZZ CS4336-KS CS4346-CZZ CS4338-KS CS4348-CZZ CS4334-BS CS4344-DZZ CS4334-DS CS4344-DZZ
8.2
Selection Guide
The CS4344 family differs by Serial Audio format as follows: * * * * CS4344 -- 16 to 24-bit, IS CS4345 -- 16 to 24-bit, Left-Justified CS4346 -- 24-bit, Right-Justified CS4348 -- 16-bit, Right-Justified
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23
CS4344/5/6/8 9. REVISION HISTORY
Release
PP3
Date
August 2005
Changes
Corrected THD+N Typ and Max performance -Updated Passband and Frequency Response specifications in "Combined Interpolation & On-chip Analog Filter Response" on page 7 -Updated PSRR specification -Updated VIH specification -Updated figures in "Filter Plots" on page 18
F1
September 2005
Contacting Cirrus Logic Support
For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com/corporate/contacts/sales.cfm
IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logo designs , and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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DS613F1

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